The present invention relates to a configurable logic device.
Reconfigurable systems, like Field-Programmable Gate Arrays (FPGAs), are capable of combining the flexibility of software with the performance of hardware. Modern FPGAs provide several thousands of logic cells that allow mapping of complex algorithms directly to hardware. If maximum hardware performance is not demanded within a given application, its execution can be split-up in time such that partitions (constituting the entire application) are subsequently executed on a reduced number of logic cells. This well-known space-time computing approach is widely used in general-purpose reconfigurable computing at algorithmic level. The hierarchical architecture of some FPGA families, where logic blocks are grouped into clusters that can implement small to mid-range logic functions spatially, facilitates such space-time algorithmic approaches. Such an architecture is described for example by Mirksy, E. A. et. all. in “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources.” In J. M. Arnold, K. L. Pocek (eds.) “Proceedings of the IEEE Workshop on FPGA for Custom Computing Machines”, IEEE 1996, pp. 157-166. In this article they describe how a convolution task is implemented by various algorithms including a systolic implementation, a micro coded implementation, a custom VLIW (horizontal micro code) implementation and a VLIW/MSIMD implementation.